The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to testing and analysis of semiconductor dies involving the alteration of the timing margin of the die.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. As clock frequencies increase, problems associated with the proper timing of various semiconductor die operations increase.
A by-product of such high-density and high functionality is an increased demand for products employing these microprocessors and devices for use in numerous applications. As the use of these devices has become more prevalent, the demand for faster operation and better reliability has increased. Such devices often require manufacturing processes that are highly complex and expensive.
As manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual dies are functional, it is also important to ensure that batches of dies perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Traditionally, integrated circuits have been tested using methods including directly accessing circuitry or devices within the integrated circuit. Directly accessing the circuitry is difficult for several reasons. For instance, in flip chip type dies, transistors and other circuitry are located in a very thin epitaxially grown silicon layer in a circuit side of the die. The circuit side of the die is arranged face-down on a package substrate. This orientation provides many operational advantages. However, due to the face-down orientation of the circuit side of the die, the transistors and other circuitry near the circuit side are not readily accessible for testing, modification, or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the die.
One particular type of semiconductor device structure that presents unique challenges to back side circuit analysis is silicon-on-insulator (SOI) structure. SOI involves forming an insulator, such as an oxide, over bulk silicon in the back side of a semiconductor device. A thin layer of silicon is formed on top of the insulator, and circuitry is formed over the insulator. The resulting SOI structure exhibits benefits including reduced switch capacitance, which leads to faster operation. Direct access to circuitry for analysis of SOI structure, however, involves milling through the oxide. The milling process can damage circuitry or other structure in the device. Such damage can alter the characteristics of the device and render the analysis inaccurate. In addition, the milling process can be time-consuming, difficult to control, and thus expensive.
Various characteristics of integrated circuit dies affect their reliability, speed and cost. One type of characteristics that are important for many reasons is the timing characteristics of a die. When a die is operated, the timing, of the operation of various portions of the circuitry is selected for the performance of selected operations. Many circuits and the functions that are performed using the circuits can withstand slight variations in timing. However, if the timing is different from what the die is designed to operate under, the operation of the die can be greatly affected. If the die is defective or if there is a design defect, even a slight delay or advance in a timing cycle can cause the die to malfunction in the defective region. These defects narrow the timing operation window of the die and effectively can cause die malfunctions at a higher rate than otherwise would occur. Therefore, identifying the defects and analyzing the die therefrom would be beneficial for addressing the challenges presented by potential defects.
The difficulty, cost, and destructive aspects of existing methods for testing integrated circuits present challenges to the growth and improvement of semiconductor technologies involving SOI structure.
The present invention is directed to a method and system for analyzing a semiconductor die having silicon-on-insulator (SOI) structure in a manner that addresses the above-mentioned challenges. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor die having SOI structure and circuitry in a circuit side opposite a back side is analyzed. A portion of substrate is removed from a back side of the semiconductor die, and the die is operated at a near a state-changing transition between a failed mode and a recovered mode. While the die is being operated, an electron-beam probe is directed at the thinned back side of the die to electrically couple a capacitance load to underlying circuitry via the insulator of the SOI structure. The capacitance load alters the timing margin of a portion of the circuitry, and the altered timing margin causes the die to undergo a state-changing transition. A response related to the transition is detected and is used to analyze the die. In a more particular example embodiment of the present invention, the detected response is used to identify a portion of the circuitry that exhibits a failure rate in response to the altered timing margin that is greater than the failure rate of other portions of circuitry in the die.
According to another example embodiment of the present invention, a system is adapted for analyzing a semiconductor die having silicon-on-insulator (SOI) structure and circuitry in a circuit side opposite a back side. The system includes a power supply adapted to operate the die near a state-changing transition between a failed mode and a recovered mode. A probe is adapted to probe the thinned back side of the die to electrically couple a capacitance load to underlying circuitry via the insulator of the SOI structure. The capacitance load alters the timing margin of the circuitry and thereby causes the circuitry to undergo a state-changing transition. A detector is adapted to detect a response from the circuitry, wherein the response is indicative of the region of the circuitry undergoing the state-changing transition, and to analyze the die therefrom.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.